1. &lt;Field of the Invention&gt;
The present invention relates to a multicomputer system having dual common memories. More particularly, it relates to a multicomputer system wherein debug by a certain computer can be readily performed by utilizing the stored contents for online processing and without destroying the stored contents when another computer is executing the online processing by the use of a common memory.
2. &lt;Prior Art&gt;
A multicomputer system having dual common memories has been known from the official gazette of Japanese Laid-open Patent Application No. 52-123137 (entitled "Dual Memory Control System", invented by KOBAYASHI et al).
According to this system, each of the dual memory devices transmits a signal indicating whether or not the memory device itself is normal and a signal indicating whether or not it is requesting maintenance. On the other hand, each CPU transmits a flag indicating whether a program being currently run is a maintenance program or an ordinary program. In the control of access to the dual common memories, in case of the maintenance program, only the memory device which is requesting the maintenance is accessed so as to prevent the destruction of the content of the normal memory device, while in case of the ordinary program, only the normal memory device is accessed (both the memory devices are accessed when they are normal).
In such multicomputer system, there is the need that, while an online operation is being performed with a certain CPU, the alterations and debug of a program are to be done with another CPU without the risk of hampering the online operation.
It has hitherto been common practice to meet the need by completely isolating the common memories.
More specifically, the respective CPUs store an access mode of either online access or debug access, while the respective common memories store a function mode of either online mode or debug mode. When the mode of access from the CPU is in agreement with the function mode of the common memory, the access is valid, and when they are not in agreement, the access is invalid. Consequently, the CPU storing the online access is accessible to only the common memory storing the online mode, and the CPU storing the debug access is accessible to only the common memory storing the debug mode.
With such measure, the CPU to perform the debug access cannot access the common memory of the online mode and so there is no fear to erroneously destroy the content thereof and to impede the online operation.
The prior-art example, however, has two disadvantages as described below.
As one of them, in a system having input/output equipment (hereinbelow, termed "common I/O" which can be controlled by both of two CPUs, it becomes difficult that the CPU under debug uses the common I/O and that the online CPU is backed up when down. The reason is that, when the common memories are completely isolated for the online CPU and the debug CPU, an operating system program cannot handle common I/O management information and operation mode information on the common memories in common.
The other disadvantage is that the debug program cannot view the information of the online operation. In case of a plant control, when a program is to be partly reorganized and then debugged, it is wished to assure that the control program can follow properly on the basis of input information from a plant as formed on the common memories by the online CPU. With the prior-art example, the assurance is difficult to be realized.
As another known example, there is a system disclosed in the official gazette of Japanese Laid-open Patent Application No. 56-14364 (entitled "Common Memory Control System", invented by NOGUCHI et al.).
Here are taught A-type common memories and B-type common memories which are respectively accessible from a plurality of CPUs. The A-type common memory permits a read/write operation from the CPU in an online condition. The B-type common memory permits a read/write operation from the offline CPU, and also permits only a write operation from the CPU in the online condition.
Since, with this measure, the A-type common memory is not accessed by the offline CPU, the online CPU does not have its operation hampered by the offline CPU. Moreover, since the B-type common memory has the writing operation performed by the online CPU, the software of the offline CPU can be developed using the status information of the online control system, so that the software can be rendered "online" stepwise.
This prior-art system, however, does not include any common data area in which both the online CPU and the offline CPU can read/write and cannot realize a common I/O control or a system setup control.